The present invention relates to a layout method of a wiring pattern in LSI circuit layout design. In particular, the present invention relates to a layout method which realizes, with short paths, a layout (arrangement) of wiring patterns for connection of elements between which there is a relatively long distance on the LSI, without relying on wires extending over a wide range on the LSI (wires which go around a wide range), and accordingly, without relying on wires of a long path length (connecting path length between elements).
In conventional LSI circuit layout design, logic circuit data is inserted in software exclusively used for layouts, and a macro cell circuit pattern (corresponding to a RAM, an IP or the like) or a xe2x80x9cpartxe2x80x9d pattern such as a standard cell circuit pattern or the like is obtained as the output. (Hereinafter, these patterns will be called macro cells and standard cells, respectively.) Then, first, these cells are arranged.
Next, a power source wiring pattern is arranged. Thereafter, among the wiring patterns (which will be called xe2x80x9cwiresxe2x80x9d hereinafter for the sake of simplicity), a clock wiring pattern (which will be called xe2x80x9cclock wirexe2x80x9d hereinafter for the sake of simplicity), which is a wiring pattern having high priority (high wire priority), is arranged.
At the wires having a lower priority than the clock wire, after the clock wire has been arranged, the contact points (starting point and ending point) and the general wiring path of wires extending over a wide range on the LSI (which are accordingly wires of a long path length) are specified, and the wires extending over a wide range on the LSI are arranged at the same time as the short wires or the wires of average lengths.
In the above-described LSI circuit pattern layout method, blocks of a circuit pattern, such as hard macro cells, for example, the RAM, the ROM and standard cells, are already arranged in the initial stages. Thus, the wires which extend over a wide range of the LSI are disposed so as to detour around these blocks. As a result, problems arise in that the wiring delay and slew rate (distortion) become large, and misoperation at the time of operation of the LSI arises, or it is easy to be affected by noise from other signals. These problems also become a cause of a decrease in the yield during the LSI manufacturing process.
At the wires which extend over a wide range on the LSI, there are many cases in which the wires which are connected to the same macro cell or to the same type of standard cells are disposed such that the logical connection relationships with other circuit patterns (hereinafter simply called xe2x80x9cconnection relationshipsxe2x80x9d) are such that the same wires are bundled together. At the time of LSI operation, these bundled wires logically propagate signals for the same operation, and thus, each of these wires must exhibit the same wire delay. However, in the conventional LSI wiring pattern layout method, the general wire paths are specified, and it is not always the case that each of the wires extending over a wide region on the LSI are disposed adjacent to one another. Thus, the signal propagation time of each wire differs. A signal, which must reach the connection destinations of the respective wires at the same time, reaches the connection destinations at different times, which is a cause for misoperation of the LSI. If such a problem arises, either the logic circuit data inputted to the software exclusively used for layout must be corrected, or the layout must be redesigned. As a result, a problem arises in that the development TAT of the LSI is long. In particular, in LSI technology of a generation in which the design rule is 0.25 microns or less, the effect of correcting the data or redesigning the layout during the LSI development TAT is great.
Problems such as those described above rarely occur with wires which connect interior cells of the same block. This is because the wire path length usually is short. However, with wires which extend over a wide range on the LSI, such as wires which connect a block to another block, it should be kept in mind that the problems described above are marked.
In order to overcome the above-described problems, a wiring layout between blocks in an LSI which is a first aspect of the present invention comprises: a plurality of connecting portion cells having a same internal wiring pattern, each of the plurality of connecting portion cells being disposed adjacent to one of the blocks; a plurality of wire portions having first and second end portions, a first end portion of each of the wire portions being disposed adjacent to one of the plurality of connecting portion cells; and at least one switch box cell, and second end portions of at least two wire portions which are disposed continuously from any block of the blocks, are adjacent to each of the switch box cells.
Here, each of the plurality of wire portions is formed from a plurality of wire portion cells having a same internal wiring pattern, and among the plurality of wire portion cells, one wire portion cell which is positioned at the first end portion of the wire portion is disposed adjacent to one of the plurality of connecting portion cells, and other wire portion cells are continuous with a wire portion cell adjacent to the connecting portion cell and are arranged in a direction of moving away from the connecting portion cell.
Further, each of the plurality of connecting portion cells includes wiring patterns, which are formed from a first or a second wiring layer and which are of a number which is equal to a number of wiring bits, and a plurality of first contact hole patterns which are for electrical connection with adjacent blocks; each of the plurality of wire portion cells includes wiring patterns which are formed from a first or a second wiring layer and are of a number which is equal to the number of wiring bits; and the wiring patterns, which are included in the plurality of wire portion cells which form at least one wire portion among at least two wire portions which are adjacent to the at least one switch box cell, are formed from the first wiring layers, and all of the wiring patterns, which are included in the plurality of wire portion cells which form other wire portions, are formed from the second wiring layers, and the switch box cell includes first wiring patterns, which intersect one another and are of a number equal to a number of wiring bits formed from the first wiring layers, and second wiring patterns of a number equal to a number of wiring bits formed from the second wiring layers, and second contact hole patterns of a number equal to the number of wiring bits, which second contact hole patterns are for electrically connecting the second wiring patterns and the first wiring patterns corresponding to respective bits.
Due to the above-described layout structure, the wires corresponding to the respective bits are arranged in a state of all being bundled together, and the problem of skewing between bits does not arise.
Further, a method of designing a wiring layout between blocks in an LSI of a second aspect of the present invention comprises the steps of: (a) extracting, from logic circuit data, blocks, macro cells, and logic blocks which are to become standard cell groups (which are sets of standard cells); (b) preparing a floor plan by analyzing bus lines connecting respective logic blocks which are extracted; (c) between blocks, preparing macros for wiring which are formed from connecting portion cells, which connect the respective blocks and wires, and switch box cells, which change directions and layers of the wires, and inserting the macros for wiring into a net list; (d) temporarily arranging the macro cells, the blocks and the standard cell groups; (e) determining an arrangement of wire portion cells which define wires of regions other than the connecting portion cells and the switch box cells, wherein a number of wire portion cells which are arranged is determined by the following formulas from an allowable value of a path delay value of the wires:
(number of wire portion cells)=(path delay value of wires)/(wire delay of 1 wire portion cell)xe2x80x83xe2x80x83(formula 1)
(wire delay of 1 wire portion cell)=(wire resistance)*(wire capacity)xe2x80x83xe2x80x83(formula 2)
(f) arranging block connecting portion cells adjacent to the respective macro cells; (g) arranging the wire portion cells continuously such that a wire path is a shortest distance, wherein in a case in which a change in a wire direction is required, the switch box cells are arranged and a direction of the wires is changed; (h) computing an overall wire length, and judging whether a path delay value of the wires falls within a range of allowable values; (i) when the overall wire length is too long and results of determination in (h) are affirmative, changing an arrangement of the wire portion cells; (j) repeating steps (g) through (i) until the path delay of the wires falls within the range of allowable values; (k) changing arrangement positions of the macro cells, the blocks, and the standard cell groups which were temporarily arranged, so as to suit a wiring layout; (l) at an interior of each standard cell group, determining an arrangement of cells within the group so as to reshape the overall shape of the group and reduce empty regions; (m) carrying out power source wiring; (n) carrying out clock tree synthesis; and (o) arranging signal wires.
Due to the above-described method of designing a layout, because the path delay of the bus line is considered from the initial stages of designing, highly accurate designing is possible.
Further, a third aspect of the present invention is a method of designing a conductive pattern layout between a plurality of blocks in an LSI, the conductive pattern transferring data from one block to the other blocks, comprising: (a) extracting the blocks from logic circuit data; (b) preparing a floor plan which defines a provisional arrangement of the blocks; (c) arranging a plurality of conductive pattern cells between the plurality of blocks after preparing the floor plan; (d) re-arranging the blocks on the basis of the arrangement of the conductive pattern cells; (e) arranging a plurality of power source patterns; and (g) arranging a plurality of signal patterns.